Numerous electric or integrated electronic circuits include PLL devices as frequency synthesizers. FIG. 1 is a block diagram of such a PLL device that comprises the following:                a phase comparator 1, denoted PHASE_COMP and possibly comprising a charge pump, and having a first comparator input 1a intended for receiving a reference signal comprised of a reference cycle that is repeated at a reference frequency denoted FREF, a second comparator input 1b for receiving a frequency-converted signal, and a comparator output 1c that is adapted for producing an error signal representative of a phase time-shift existing between the reference signal and the frequency-converted signal;        a loop filter 2, having a filter input 2a that is connected to the comparator output 1c, and suitable for producing a control voltage based on a time-filtering of the error signal at a filter output 2b;         a voltage-controlled oscillator (VCO) module 3, having a control input 3a connected to the filter output 2b, and a VCO output 3c for producing a VCO signal that has a VCO frequency denoted FVCO and varying as a function of the control voltage; and        a frequency divider 4, which is denoted F_DIVIDER, and is connected at a divider input 4a to the VCO output 3c, and adapted for producing at a divider output 4c the frequency-converted signal based on the VCO signal, this divider output 4c being connected to the second comparator input 1b.         
The reference signal may be supplied by any reference clock module 10, denoted REF_CLOCK. The reference clock module 10 may be contained within a same integrated circuit chip as the PLL device, or may be external to such chip.
The phase comparator 1 and the loop filter 2 may be of any type known, analog or digital. In particular, for analog implementations, the phase comparator 1 may be comprised of a phase-frequency detector combined downstream with a charge pump. Digital implementations of the loop filter 2 may include a digital-to-analog converter so that the control voltage, which is fed into the control input 3a of the VCO module 3, is always an analog direct signal, similar to the analog implementations of the loop filter 2.
The VCO module 3 may also be of any type known, including without limitation, VCO modules that are provided with frequency range selection. Such a VCO module commonly comprises a capacitor bank (not shown) which produces a capacitance value selected by a digital word fed into an additional input 3b of the VCO module 3. Selecting the capacitance value in this way makes the FVCO-frequency vary limitedly within a reduced frequency range when the control voltage, which is denoted Vtune, is varied at the control input 3a. Thus, the frequency range is selected by the digital word fed into the additional input 3b, and the value of the FVCO-frequency is controlled within this frequency range by tuning the Vtune-voltage. Such selection of the FVCO-frequency range is commonly called VCO calibration, and may be performed using a dedicated unit 30 for selecting the digital word.
The frequency-converted signal is denoted as F-converted signal. It is produced by the frequency divider 4 from the VCO signal received at the divider input 4a so that the F-converted signal has a synthesized frequency FDIV, which equals the FVCO-frequency divided by a division ratio value N. Actually, due to the N-value possibly being a non-integer, the frequency divider 4 is fed appropriately with an instant value as the division ratio N, so that a time-average of the synthesized frequency FDIV matches a result of the FVCO-frequency divided by N. In a known manner, the instant value used as the division ratio may be produced by combining an integer part of N with a modulated sequence corresponding to a fractional part of N. The modulated sequence may be produced by an interpolator 41, for example, a sigma-delta modulator, and combined with the integer part using a combiner 40. The output of the combiner 40 may be connected to an additional divider input 4b that is dedicated to receive the instant value of the division ratio.
The phase comparator 1, the loop filter 2, the VCO module 3 and the frequency divider 4 form the PLL loop. According to well-known PLL operation, the voltage Vtune results from the time-filtering of the error signal, the F-converted signal results from the N-division of the frequency FVCO of the VCO signal, and the F-converted signal is matched in phase with the reference signal. Also in a known manner, such operation of the PLL device may be monitored by a lock detector (not shown), which tests continually a lock condition for indicating whether the frequency FDIV of the F-converted signal remains very close to the reference frequency FREF. Such operation is commonly called lock acquisition step, leading to the lock condition being met. Once the lock condition is met, the VCO signal is frequency-elevated with respect to the reference signal according to the equation: FVCO≈FREF×N. This is the locked operation of the PLL device, and reducing the duration of the lock acquisition step is an important issue for many applications of the PLL devices.
After the VCO calibration has been performed correctly, both frequencies FDIV and FREF are close to one another thanks to the appropriate selection of the FVCO-frequency range that has reduced range length. But the phase time-shift that exists between the F-converted signal and the reference signal is uncontrolled at that time. Actually, the modulated sequence that is fed into the additional divider input 4b is generated taking into account a target value for the time-shift to exist between the respective phases of the F-converted signal and the reference signal. This target value is called phase parameter and denoted PHASE in the figures. Then, the lock acquisition step results in increasing or decreasing slightly the frequency FDIV of the F-converted signal so that the time-shift that actually exists between the phases of the F-converted signal and the reference signal converges in time towards the phase parameter value.
But, for reducing the noise that may impact the PLL loop operation, a gain value of the open PLL loop that is effective during the lock acquisition step is selected to be low, sometimes even very low. The gain value is the ratio between a variation in the FDIV-frequency of the F-converted signal and the variation of the Vtune-voltage that produces the FDIV-variation. It results from the low gain value that much time during the lock acquisition step may be needed for the time-shift that actually exists between the phases of the F-converted signal and the reference signal to match the phase parameter value.
The present invention solves the disadvantages of the prior art by disclosing a device that reduces the duration until the lock condition is met, so-called lock time, for a PLL device which starts operating or recovers the lock state after it has been lost. This first object of lock time reduction applies in particular for a PLL device which is operated with a low value for the open PLL loop gain.
Furthermore, the present invention also operates simultaneously several PLL devices using a single reference signal, while ensuring that desired time-shifts actually exist between the respective F-converted signals of the PLL devices.